fpga板上的输出引脚状态是什么

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如果引脚未连接到FPGA封装内部，请不要将其连接到PCB上的任何内容。如果您的设计未使用该引脚，也不要将其连接到PCB上的任何内容。

这些工具将在所有未使用的IO引脚上实例化内部上拉，您不必担心，我们会为您处理。

此外，对使用的任何输入引脚都没有任何伤害，并且悬空。

Noite确定您过去遇到的“噪音”问题，但FPGA设备设计用于处理所有IO引脚上的中间电压，这在许多应用中通常都存在。

取一些未使用的IO引脚，并将它们连接到接头或引脚字段非常有用，这样当您需要调试时，您可以轻松地将信号路由到这些备用引脚之一。

谢谢和RegardsBalkrishan -----------------------------------------------

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以上来自于谷歌翻译

以下为原文

If the pin is unconnected internal to the FPGA package, do not connect it to anything on your pcb.

If the pin is unused by your design, also do not connect it to anything on your pcb.  The tools will instantiate an internal pullup on all unused IO pins, you do not have to worry about it, we take care of it for you.  Also, no harm is done to any input pin that is used, and left floating.  Noite sure what "noise" issues you have had in the past, but the FPGA device is designed to handle intermediate voltages on all IO pins asa that is normally present in many applications.

It is very useful to take a number of unused IO pins, and wire them to a header, or a pin field, so that when you need to debug, you may easily route a signal out to one of these spare pins.

Thanks and Regards

Balkrishan

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